using VHDL-trigger circuit stability, steady time for the whole system clock several times.

pluse_delay
...........\LIB.DLS
...........\pluse_delay.acf
...........\pluse_delay.fit
...........\pluse_delay.hex
...........\pluse_delay.hif
...........\pluse_delay.mmf
...........\pluse_delay.ndb
...........\pluse_delay.pin
...........\pluse_delay.pof
...........\pluse_delay.rpt
...........\pluse_delay.scf
...........\pluse_delay.snf
...........\pluse_delay.sof
...........\PLUSE_DELAY.sym
...........\pluse_delay.ttf
...........\pluse_delay.vhd
...........\U0770890.DLS
...........\U3633468.DLS
...........\U8440066.DLS

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