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Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 2.52mb
- Downloaded :0次
- Author :陈****
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Design a linear phase FIR filter (31 bands) 8 input, 8 output, H (n) = (1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69111128111, ... ... 2,1) H (n) has a symmetry. Input signal range [± 99,0,0,0, ± 70,0,0,0, ± 99,0,0,0, ± 70, ...]
Packet file list
(Preview for download)
FIR31
.....\chip_editor.acv
.....\cmp_state.ini
.....\db
.....\..\add_sub_cfh.tdf
.....\..\add_sub_dhh.tdf
.....\..\add_sub_efh.tdf
.....\..\add_sub_ffh.tdf
.....\..\add_sub_tdh.tdf
.....\..\fir31-sim.vwf
.....\..\fir31.asm.qmsg
.....\..\fir31.cmp.cdb
.....\..\fir31.cmp.ddb
.....\..\fir31.cmp.hdb
.....\..\fir31.cmp.rdb
.....\..\fir31.cmp.tdb
.....\..\fir31.csf.qmsg
.....\..\fir31.db_info
.....\..\fir31.DDB
.....\..\fir31.fir31.sld_design_entry.sci
.....\..\fir31.fit.qmsg
.....\..\fir31.fld
.....\..\fir31.fnsim.cdb
.....\..\fir31.fnsim.hdb
.....\..\fir31.frm.hdb
.....\..\fir31.fsf.qmsg
.....\..\fir31.hif
.....\..\fir31.icc
.....\..\fir31.map.cdb
.....\..\fir31.map.hdb
.....\..\fir31.map.qmsg
.....\..\fir31.pre_map.hdb
.....\..\fir31.project.hdb
.....\..\fir31.rpp.qmsg
.....\..\fir31.rtlv.hdb
.....\..\fir31.rtlv_rvd.rvd
.....\..\fir31.rtlv_sg.cdb
.....\..\fir31.rtlv_sg_swap.cdb
.....\..\fir31.sgdiff.cdb
.....\..\fir31.sgdiff.hdb
.....\..\fir31.signalprobe.cdb
.....\..\fir31.sim.hdb
.....\..\fir31.sim.qmsg
.....\..\fir31.sim.rdb
.....\..\fir31.tan.qmsg
.....\..\fir311
.....\..\......\fir31.cmp.ddb
.....\..\......\fir311.DDB
.....\..\fir31_cmp.qrpt
.....\..\fir31_hier_info
.....\..\fir31_sim.qrpt
.....\..\fir31_syn_hier_info
.....\..\mux_7ac.tdf
.....\dff1
.....\....\cmp_state.ini
.....\....\db
.....\....\..\dff1-sim.vwf
.....\....\..\dff1.asm.qmsg
.....\....\..\dff1.cmp.cdb
.....\....\..\dff1.cmp.ddb
.....\....\..\dff1.cmp.hdb
.....\....\..\dff1.cmp.rdb
.....\....\..\dff1.cmp.tdb
.....\....\..\dff1.csf.qmsg
.....\....\..\dff1.db_info
.....\....\..\dff1.dff1.sld_design_entry.sci
.....\....\..\dff1.fit.qmsg
.....\....\..\dff1.hif
.....\....\..\dff1.icc
.....\....\..\dff1.map.cdb
.....\....\..\dff1.map.hdb
.....\....\..\dff1.map.qmsg
.....\....\..\dff1.pre_map.hdb
.....\....\..\dff1.project.hdb
.....\....\..\dff1.rtlv.hdb
.....\....\..\dff1.rtlv_sg.cdb
.....\....\..\dff1.rtlv_sg_swap.cdb
.....\....\..\dff1.sgdiff.cdb
.....\....\..\dff1.sgdiff.hdb
.....\....\..\dff1.signalprobe.cdb
.....\....\..\dff1.sim.hdb
.....\....\..\dff1.sim.qmsg
.....\....\..\dff1.sim.rdb
.....\....\..\dff1.tan.qmsg
.....\....\..\dff1_cmp.qrpt
.....\....\..\dff1_hier_info
.....\....\..\dff1_sim.qrpt
.....\....\..\dff1_syn_hier_info
.....\....\dff1.asm.rpt
.....\....\dff1.done
.....\....\dff1.fit.eqn
.....\....\dff1.fit.rpt
.....\....\dff1.flow.rpt
.....\....\dff1.map.eqn
.....\....\dff1.map.rpt
.....\....\dff1.pin
.....\....\dff1.pof
.....\....\dff1.qpf
.....\....\dff1.qsf
.....\....\dff1.qws
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