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equlizer

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 23kb
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  • Author :陈***
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Introduction - If you have any usage issues, please Google them yourself
equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integrated RTL circuit which contains 3 module FILTER, ERR_DECISION, ADJUST hope useful for all.
Packet file list
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equlizer
........\accumulator.vhd
........\adjust.vhd
........\adjust1_mult.vhd
........\adjust2_mult.vhd
........\adjust3_mult.vhd
........\adjust_con.vhd
........\cmplcode2.vhd
........\equ_pak.vhd
........\err_decion.vhd
........\filter.vhd
........\filter3_coef.vhd
........\filter_add.vhd
........\filter_coef.vhd
........\filter_coef1.vhd
........\filter_con.vhd
........\filter_shift.vhd
........\mult2.vhd
........\mult3.vhd
........\p_s.vhd
........\shift3.vhd
........\s_term1.vhd
........\s_term2.vhd
........\s_term3.vhd
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