a graduate design of the FPGA using VHDL prepared

full_featured
.............\altera_vhdl_support.vhd
.............\bht_ram.mif
.............\bswap_cpu.vhd
.............\button_pio.vhd
.............\cmp_state.ini
.............\connector_pll.bsf
.............\connector_pll.cmp
.............\connector_pll.inc
.............\connector_pll.v
.............\connector_pll_bb.v
.............\connector_pll_inst.v
.............\cpu.ocp
.............\cpu.vhd
.............\cpu_gen_log_0.txt
.............\cpu_jtag_debug_module.vhd
.............\cpu_jtag_debug_module_wrapper.vhd
.............\cpu_ociram_default_contents.mif
.............\cpu_test_bench.vhd
.............\db
.............\..\full_featured.cmp.rdb
.............\..\full_featured.db_info
.............\..\full_featured.eco.cdb
.............\..\full_featured.hif
.............\..\full_featured.map.hdb
.............\..\full_featured.map.qmsg
.............\..\full_featured.sld_design_entry.sci
.............\..\full_featured.sld_design_entry_dsc.sci
.............\..\full_featured_cmp.qrpt
.............\dc_tag_ram.mif
.............\delay_reset_block.bdf
.............\delay_reset_block.bsf
.............\dma.vhd
.............\epcs_controller.vhd
.............\epcs_controller_boot_rom.hex
.............\full_1c20.bsf
.............\full_1c20.ptf
.............\full_1c20.ptf.4.01
.............\full_1c20.vhd
.............\full_1c20_generation_script
.............\full_1c20_log.txt
.............\full_1c20_setup_quartus_native_synthesis.tcl
.............\full_1c20_sim
.............\.............\atail-f.pl
.............\.............\jtag_uart_input_mutex.dat
.............\.............\jtag_uart_input_stream.dat
.............\.............\jtag_uart_output_stream.dat
.............\.............\uart1_input_data_mutex.dat
.............\.............\uart1_input_data_stream.dat
.............\.............\uart1_log_module.txt
.............\full_featured.asm.rpt
.............\full_featured.bdf
.............\full_featured.done
.............\full_featured.fit.rpt
.............\full_featured.flow.rpt
.............\full_featured.map.rpt
.............\full_featured.map.summary
.............\full_featured.pin
.............\full_featured.pof
.............\full_featured.qpf
.............\full_featured.qsf
.............\full_featured.qws
.............\full_featured.sof
.............\full_featured.tan.rpt
.............\full_featured.tan.summary
.............\full_featured_assignment_defaults.qdf
.............\full_featured_compile_.log
.............\high_res_timer.vhd
.............\ic_tag_ram.mif
.............\jtag_uart.vhd
.............\lcd_display.vhd
.............\led_pio.vhd
.............\reconfig_request_pio.vhd
.............\reset_counter.bsf
.............\reset_counter.v
.............\rf_ram_a.mif
.............\rf_ram_b.mif
.............\sdram.vhd
.............\sdram_pll.bsf
.............\sdram_pll.cmp
.............\sdram_pll.inc
.............\sdram_pll.v
.............\sdram_pll_bb.v
.............\sdram_pll_inst.v
.............\sdram_test_component.vhd
.............\serv_req_info.txt
.............\seven_seg_pio.vhd
.............\sopc_builder_debug_log.txt
.............\sysid.vhd
.............\sys_clk_timer.vhd
.............\uart1.vhd

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