with Verilog HDL language written on display in the pattern of the source

vga
...\cmp_state.ini
...\db
...\..\add_sub_llh.tdf
...\..\add_sub_plh.tdf
...\..\vga.asm.qmsg
...\..\vga.cbx.xml
...\..\vga.cmp.cdb
...\..\vga.cmp.hdb
...\..\vga.cmp.rdb
...\..\vga.cmp.tdb
...\..\vga.cmp0.ddb
...\..\vga.db_info
...\..\vga.eco.cdb
...\..\vga.fit.qmsg
...\..\vga.hier_info
...\..\vga.hif
...\..\vga.map.cdb
...\..\vga.map.hdb
...\..\vga.map.qmsg
...\..\vga.pre_map.cdb
...\..\vga.pre_map.hdb
...\..\vga.psp
...\..\vga.rtlv.hdb
...\..\vga.rtlv_sg.cdb
...\..\vga.rtlv_sg_swap.cdb
...\..\vga.sgdiff.cdb
...\..\vga.sgdiff.hdb
...\..\vga.sld_design_entry.sci
...\..\vga.sld_design_entry_dsc.sci
...\..\vga.syn_hier_info
...\..\vga.tan.qmsg
...\..\vga_cmp.qrpt
...\vga.asm.rpt
...\vga.done
...\vga.fit.eqn
...\vga.fit.rpt
...\vga.fit.summary
...\vga.flow.rpt
...\vga.map.eqn
...\vga.map.rpt
...\vga.map.summary
...\vga.pin
...\vga.pof
...\vga.qpf
...\vga.qsf
...\vga.qws
...\vga.sof
...\vga.tan.rpt
...\vga.tan.summary
...\vga.v

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