hard work for Dictyophora development. . We hope that the right useful.

DE2_control_panel
.................\db
.................\..\de2.cbx.xml
.................\..\de2.cmp.qrpt
.................\..\de2.cmp.rdb
.................\..\de2.db_info
.................\..\de2.eco.cdb
.................\..\de2.hif
.................\..\de2.map.hdb
.................\..\de2.map.qmsg
.................\..\de2.sld_design_entry.sci
.................\..\de2.sld_design_entry_dsc.sci
.................\..\DE2_USB_API.cbx.xml
.................\..\DE2_USB_API.cmp.qrpt
.................\..\de2_usb_api.cmp.rdb
.................\..\de2_usb_api.db_info
.................\..\de2_usb_api.eco.cdb
.................\..\DE2_USB_API.hif
.................\..\de2_usb_api.map.hdb
.................\..\de2_usb_api.map.qmsg
.................\..\de2_usb_api.sld_design_entry.sci
.................\..\de2_usb_api.sld_design_entry_dsc.sci
.................\de2.flow.rpt
.................\de2.map.rpt
.................\de2.map.summary
.................\de2.qpf
.................\de2.qsf
.................\de2.qws
.................\DE2_Control_Panel.exe
.................\DE2_USB_API.cdf
.................\DE2_USB_API.flow.rpt
.................\DE2_USB_API.map.rpt
.................\DE2_USB_API.map.summary
.................\DE2_USB_API.pof
.................\de2_usb_api.qpf
.................\de2_usb_api.qsf
.................\DE2_USB_API.qws
.................\DE2_USB_API.sof
.................\FTD2XX.DLL
.................\Image_Convert_English.pdf
.................\ImgConv.exe
.................\nios32.ptf
.................\nios32.ptf.bak
.................\nios32.v
.................\nios32.vhd
.................\sopc_builder_debug_log.txt
DE2_lab_exercises
.................\DE2_labs_verilog
.................\................\lab10_Verilog.pdf
.................\................\lab1_Verilog.pdf
.................\................\lab2_Verilog.pdf
.................\................\lab3_Verilog.pdf
.................\................\lab4_Verilog.pdf
.................\................\lab5_Verilog.pdf
.................\................\lab6_Verilog.pdf
.................\................\lab7_Verilog.pdf
.................\................\lab8_Verilog.pdf
.................\................\lab9_Verilog.pdf
.................\DE2_labs_vhdl
.................\.............\lab10_VHDL.pdf
.................\.............\lab1_VHDL.pdf
.................\.............\lab2_VHDL.pdf
.................\.............\lab3_VHDL.pdf
.................\.............\lab4_VHDL.pdf
.................\.............\lab5_VHDL.pdf
.................\.............\lab6_VHDL.pdf
.................\.............\lab7_VHDL.pdf
.................\.............\lab8_VHDL.pdf
.................\.............\lab9_VHDL.pdf
.................\DE2_pin_assignments.csv
DE2_schematics
..............\DE2_outline.pdf
..............\DE2_schematics.pdf
DE2_tutorials
.............\design_files
.............\............\addersubtractor.v
.............\............\addersubtractor.vhd
.............\............\addersubtractor2.v
.............\............\addersubtractor2.vhd
.............\............\DE2_pin_assignments.csv
.............\tut_initialDE2.pdf
.............\tut_lpms_verilog.pdf
.............\tut_lpms_vhdl.pdf
.............\tut_quartus_intro_schem.pdf
.............\tut_quartus_intro_verilog.pdf
.............\tut_quartus_intro_vhdl.pdf
.............\tut_simulation_verilog.pdf
.............\tut_simulation_vhdl.pdf
.............\tut_timing_verilog.pdf
.............\tut_timing_vhdl.pdf

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