Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

ls12_mux16

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 959kb
  • Downloaded :0次
  • Author :1*****
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
A 16-bit multiplier veriolog language. Use a novice.
Packet file list
(Preview for download)


ls12_mux16\16位乘法器算法解析.txt
..........\db\mux16.asm.qmsg
..........\..\mux16.cbx.xml
..........\..\mux16.cmp.bpm
..........\..\mux16.cmp.cdb
..........\..\mux16.cmp.ecobp
..........\..\mux16.cmp.hdb
..........\..\mux16.cmp.kpt
..........\..\mux16.cmp.logdb
..........\..\mux16.cmp.rdb
..........\..\mux16.cmp.tdb
..........\..\mux16.cmp0.ddb
..........\..\mux16.cmp_merge.kpt
..........\..\mux16.db_info
..........\..\mux16.eco.cdb
..........\..\mux16.eda.qmsg
..........\..\mux16.fit.qmsg
..........\..\mux16.hier_info
..........\..\mux16.hif
..........\..\mux16.map.bpm
..........\..\mux16.map.cdb
..........\..\mux16.map.ecobp
..........\..\mux16.map.hdb
..........\..\mux16.map.kpt
..........\..\mux16.map.logdb
..........\..\mux16.map.qmsg
..........\..\mux16.map_bb.cdb
..........\..\mux16.map_bb.hdb
..........\..\mux16.map_bb.hdbx
..........\..\mux16.map_bb.logdb
..........\..\mux16.pre_map.cdb
..........\..\mux16.pre_map.hdb
..........\..\mux16.psp
..........\..\mux16.rtlv.hdb
..........\..\mux16.rtlv_sg.cdb
..........\..\mux16.rtlv_sg_swap.cdb
..........\..\mux16.sgdiff.cdb
..........\..\mux16.sgdiff.hdb
..........\..\mux16.sld_design_entry.sci
..........\..\mux16.sld_design_entry_dsc.sci
..........\..\mux16.syn_hier_info
..........\..\mux16.tan.qmsg
..........\..\mux16.tis_db_list.ddb
..........\..\mux16.tmw_info
..........\..\prev_cmp_mux16.asm.qmsg
..........\..\prev_cmp_mux16.eda.qmsg
..........\..\prev_cmp_mux16.fit.qmsg
..........\..\prev_cmp_mux16.map.qmsg
..........\..\prev_cmp_mux16.qmsg
..........\..\prev_cmp_mux16.tan.qmsg
..........\incremental_db\compiled_partitions\mux16.root_partition.cmp.atm
..........\..............\...................\mux16.root_partition.cmp.dfp
..........\..............\...................\mux16.root_partition.cmp.hdbx
..........\..............\...................\mux16.root_partition.cmp.kpt
..........\..............\...................\mux16.root_partition.cmp.logdb
..........\..............\...................\mux16.root_partition.cmp.rcf
..........\..............\...................\mux16.root_partition.map.atm
..........\..............\...................\mux16.root_partition.map.dpi
..........\..............\...................\mux16.root_partition.map.hdbx
..........\..............\...................\mux16.root_partition.map.kpt
..........\..............\README
..........\mux16.asm.rpt
..........\mux16.done
..........\mux16.eda.rpt
..........\mux16.fit.rpt
..........\mux16.fit.smsg
..........\mux16.fit.summary
..........\mux16.flow.rpt
..........\mux16.map.rpt
..........\mux16.map.summary
..........\mux16.pin
..........\mux16.pof
..........\mux16.qpf
..........\mux16.qsf
..........\mux16.qws
..........\mux16.sof
..........\mux16.tan.rpt
..........\mux16.tan.summary
..........\mux16.v
..........\mux16.v.bak
..........\mux16_nativelink_simulation.rpt
..........\simulation\modelsim\modelsim.ini
..........\..........\........\msim_transcript
..........\..........\........\mux16.sft
..........\..........\........\mux16.vo
..........\..........\........\mux16.vt
..........\..........\........\mux16.vt.bak
..........\..........\........\mux16_modelsim.xrf
..........\..........\........\mux16_run_msim_rtl_verilog.do
..........\..........\........\mux16_run_msim_rtl_verilog.do.bak
..........\..........\........\mux16_v.sdo
..........\..........\........\rtl_work\mux16\verilog.psm
..........\..........\........\........\.....\_primary.dat
..........\..........\........\........\.....\_primary.dbs
..........\..........\........\........\.....\_primary.vhd
..........\..........\........\........\....._vlg_tst\verilog.psm
..........\..........\........\........\.............\_primary.dat
..........\..........\........\........\.............\_primary.dbs
..........\..........\........\........\.............\_primary.vhd
..........\..........\........\........\_info
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.