experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

lab2
....\adder4.vhd
....\addsub.vhd
....\addsubtest.vhd
....\addsub_addsubtest_vhd_tb.fdo
....\addsub_addsubtest_vhd_tb.udo
....\automake.log
....\fulladder.vhd
....\Lab 2 Adder_by.doc
....\lab2.dhp
....\lab2.npl
....\pepExtractor.prj
....\transcript
....\userlang.tpl
....\vsim.wlf
....\work
....\....\adder4
....\....\......\behavioral.asm
....\....\......\behavioral.dat
....\....\......\_primary.dat
....\....\addsub
....\....\......\behavioral.asm
....\....\......\behavioral.dat
....\....\......\_primary.dat
....\....\addsub_addsubtest_vhd_tb
....\....\........................\behavior.asm
....\....\........................\behavior.dat
....\....\........................\_primary.dat
....\....\fulladder
....\....\.........\behavioral.asm
....\....\.........\behavioral.dat
....\....\.........\_primary.dat
....\....\_info
....\xst
....\...\work
....\...\....\hdllib.ref
....\...\....\hdpdeps.ref
....\...\....\sub00
....\...\....\.....\vhpl00.vho
....\__projnav
....\.........\coregen.rsp
....\.........\createTB.err
....\.........\lab2.gfl
....\__projnav.log

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