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110detector_lab

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 140kb
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  • Author :徐****
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Introduction - If you have any usage issues, please Google them yourself
a simple survey of 110 three detectors, and a logical map vhdl description, including reports and experimental test plan.
Packet file list
(Preview for download)
lab3
....\automake.log
....\detector.cmd_log
....\detector.sch
....\detector.schbak
....\detector.schcmd
....\detector.vhf
....\Lab 3 110 Detector.doc
....\lab3.dhp
....\lab3.npl
....\pepExtractor.prj
....\results.txt
....\testwave.ANT
....\testwave.fdo
....\testwave.tbw
....\testwave.udo
....\testwave.vhw
....\transcript
....\vsim.wlf
....\work
....\....\detector
....\....\........\behavioral.asm
....\....\........\behavioral.dat
....\....\........\_primary.dat
....\....\detector_cfg
....\....\............\_primary.dat
....\....\............\_vhdl.asm
....\....\testwave
....\....\........\testbench_arch.asm
....\....\........\testbench_arch.dat
....\....\........\_primary.dat
....\....\_info
....\xst
....\...\work
....\...\....\hdllib.ref
....\...\....\hdpdeps.ref
....\...\....\sub00
....\...\....\.....\vhpl00.vho
....\...\....\.....\vhpl01.vho
....\__projnav
....\.........\coregen.rsp
....\.........\detector_jhdparse_tcl.rsp
....\.........\lab3.gfl
....\__projnav.log
lab4
....\automake.log
....\detector.ldo
....\detector.vhd
....\Lab 4 110 Detector2.doc
....\lab4.dhp
....\lab4.npl
....\pepExtractor.prj
....\results.txt
....\testwave4.ANT
....\testwave4.fdo
....\testwave4.jhd
....\testwave4.tbw
....\testwave4.udo
....\testwave4.vhw
....\transcript
....\userlang.tpl
....\vsim.wlf
....\vt.fdo
....\vt.udo
....\work
....\....\detector
....\....\........\behavioral.asm
....\....\........\behavioral.dat
....\....\........\_primary.dat
....\....\detector3
....\....\.........\behavioral.asm
....\....\.........\behavioral.dat
....\....\.........\_primary.dat
....\....\detector3_cfg
....\....\.............\_primary.dat
....\....\.............\_vhdl.asm
....\....\detector_cfg
....\....\............\_primary.dat
....\....\............\_vhdl.asm
....\....\testwave4
....\....\.........\testbench_arch.asm
....\....\.........\testbench_arch.dat
....\....\.........\_primary.dat
....\....\vt
....\....\..\testbench_arch.asm
....\....\..\testbench_arch.dat
....\....\..\_primary.dat
....\....\_info
....\xst
....\...\work
....\...\....\hdllib.ref
....\...\....\hdpdeps.ref
....\...\....\sub00
....\...\....\.....\vhpl00.vho
....\...\....\.....\vhpl01.vho
....\__projnav
....\.........\coregen.rsp
....\.........\hb_cmds
....\.........\lab4.gfl
....\__projnav.log
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