proficient VerilogHDL : IC design example explanation of the core technology

精通VerilogHDL：IC设计核心技术实例详解


......................................\习题.vsd
......................................\第9章：JPEG程序范例.doc
......................................\部分习题源码
......................................\............\ex2_2
......................................\............\.....\demux.fsdb
......................................\............\.....\ex2_2.v
......................................\............\.....\rtl_wrk
......................................\............\.....\.......\ex2_2
......................................\............\.....\.......\.....\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\_info
......................................\............\.....\run.do
......................................\............\ex2_3
......................................\............\.....\ex2_3.fsdb
......................................\............\.....\ex2_3.v
......................................\............\.....\ex2_3.v.bak
......................................\............\.....\rtl_wrk
......................................\............\.....\.......\ex2_3
......................................\............\.....\.......\.....\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\_info
......................................\............\.....\run.do
......................................\............\ex2_6
......................................\............\.....\ex2_6.fsdb
......................................\............\.....\ex2_6.v
......................................\............\.....\rtl_wrk
......................................\............\.....\.......\ex2_6
......................................\............\.....\.......\.....\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\_info
......................................\............\.....\run.do
......................................\............\ex3_3
......................................\............\.....\dff.prd
......................................\............\.....\dff.prj
......................................\............\.....\dff.v
......................................\............\.....\rev_1
......................................\............\.....\.....\dff.srr
......................................\............\.....\.....\syntmp
......................................\............\ex6_1
......................................\............\.....\comp.v
......................................\............\.....\comp4.v
......................................\............\.....\ex6_1.v
......................................\............\.....\rtl_wrk
......................................\............\.....\.......\comp
......................................\............\.....\.......\....\verilog.asm
......................................\............\.....\.......\....\_primary.dat
......................................\............\.....\.......\....\_primary.vhd
......................................\............\.....\.......\comp4
......................................\............\.....\.......\.....\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\ex6_1
......................................\............\.....\.......\.....\verilog.asm
......................................\............\.....\.......\....

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