or a Verilog source code can be run in modelsim strongly recommend downloading

Packet : 317676715.8.rar filelist
5.8\work\_info
5.8\work\tb\_primary.vhd
5.8\work\tb\verilog.asm
5.8\work\tb\_primary.dat
5.8\work\tb
5.8\work\tbsr\_primary.vhd
5.8\work\tbsr\verilog.asm
5.8\work\tbsr\_primary.dat
5.8\work\tbsr
5.8\work
5.8\vsim.wlf
5.8\tcl_stacktrace.txt
5.8\tbsr.cr.mti
5.8\tbsr.mpf
5.8\tbsr.v
5.8\tbsr.v.bak
5.8\tb.v
5.8\tb.v.bak
5.8

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