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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 55kb
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  • Author :王***
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Introduction - If you have any usage issues, please Google them yourself
the booth algorithm to implement the 32bit 's multiplication.
Packet file list
(Preview for download)
Lab2
....\ALU.vhd
....\ARegister.vhd
....\ARegister.vhd.bak
....\bmul_ser.vhd
....\bmul_ser.vhd.bak
....\Booth.cr.mti
....\Booth.mpf
....\Control.vhd
....\Counter.vhd
....\DRegister.vhd
....\DRegister.vhd.bak
....\mul32c.vhd
....\mul32c_test.vhd
....\mul_ser.vhd
....\QRegister.vhd
....\QRegister.vhd.bak
....\vish_stacktrace.vstf
....\vsim.wlf
....\work
....\....\add32csa
....\....\........\circuits.asm
....\....\........\circuits.dat
....\....\........\_primary.dat
....\....\aregister
....\....\.........\behav.asm
....\....\.........\behav.dat
....\....\.........\_primary.dat
....\....\bmul_ser
....\....\........\schematic.asm
....\....\........\schematic.dat
....\....\........\_primary.dat
....\....\dregister
....\....\.........\behav.asm
....\....\.........\behav.dat
....\....\.........\_primary.dat
....\....\fulladder
....\....\.........\structural.asm
....\....\.........\structural.dat
....\....\.........\_primary.dat
....\....\fulladder32
....\....\...........\circuits.asm
....\....\...........\circuits.dat
....\....\...........\_primary.dat
....\....\mul32c
....\....\......\circuits.asm
....\....\......\circuits.dat
....\....\......\_primary.dat
....\....\mul32c_test
....\....\...........\circuits.asm
....\....\...........\circuits.dat
....\....\...........\_primary.dat
....\....\mul_ser
....\....\.......\_primary.dat
....\....\qregister
....\....\.........\behav.asm
....\....\.........\behav.dat
....\....\.........\_primary.dat
....\....\_info
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