verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working

xcv
...\test.v
...\work
...\....\xcv
...\....\...\verilog.asm
...\....\...\_primary.dat
...\....\...\_primary.vhd
...\....\xcv_@top
...\....\........\verilog.asm
...\....\........\_primary.dat
...\....\........\_primary.vhd
...\....\_info
...\xcv.v

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