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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 153kb
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  • Author :ouyu****
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Introduction - If you have any usage issues, please Google them yourself
vhdl sequence of a Serial Signal Generator Design and Implementation
Packet file list
(Preview for download)
实验五
......\db
......\..\add_sub_3kh.tdf
......\..\produce.asm.qmsg
......\..\produce.cbx.xml
......\..\produce.cmp.cdb
......\..\produce.cmp.hdb
......\..\produce.cmp.qrpt
......\..\produce.cmp.rdb
......\..\produce.cmp.tdb
......\..\produce.cmp0.ddb
......\..\produce.dbp
......\..\produce.db_info
......\..\produce.eco.cdb
......\..\produce.eds_overflow
......\..\produce.fit.qmsg
......\..\produce.hier_info
......\..\produce.hif
......\..\produce.map.cdb
......\..\produce.map.hdb
......\..\produce.map.qmsg
......\..\produce.pre_map.cdb
......\..\produce.pre_map.hdb
......\..\produce.psp
......\..\produce.rtlv.hdb
......\..\produce.rtlv_sg.cdb
......\..\produce.rtlv_sg_swap.cdb
......\..\produce.sgdiff.cdb
......\..\produce.sgdiff.hdb
......\..\produce.sim.hdb
......\..\produce.sim.qmsg
......\..\produce.sim.qrpt
......\..\produce.sim.rdb
......\..\produce.sim.vwf
......\..\produce.sld_design_entry.sci
......\..\produce.sld_design_entry_dsc.sci
......\..\produce.syn_hier_info
......\..\produce.tan.qmsg
......\pro.vhd
......\produce.asm.rpt
......\produce.cdf
......\produce.done
......\produce.fit.eqn
......\produce.fit.rpt
......\produce.fit.summary
......\produce.flow.rpt
......\produce.map.eqn
......\produce.map.rpt
......\produce.map.summary
......\produce.pin
......\produce.pof
......\produce.qpf
......\produce.qsf
......\produce.qws
......\produce.sim.rpt
......\produce.tan.rpt
......\produce.tan.summary
......\produce.vhd
......\produce.vwf
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