Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.

exemplar.his
exemplar.log
fsm_temp.edf
fsm_temp.ncf
fsm_temp.sum
fsm_temp.xdb
news5f.cr.mti
news5f.mpf
news5f.v
news5f.v.bak
news5f_top.edf
news5f_top.ncf
news5f_top.sum
news5f_top.v
news5f_top.v.bak
news5f_top.xdb
news5f_top_0.edf
news5f_top_0.lsp
news5f_top_0.ncf
news5f_top_0.scr
news5f_top_0.sum
news5f_top_0.xdb
news5f_top_1.edf
news5f_top_1.ncf
news5f_top_1.sum
news5f_top_1.xdb
spc.edf
spc.ncf
spc.sum
spc.xdb
tb_news5f.v
vsim.wlf
work_s5f_INTERFACE_XRTL.nlv

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