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data_transfer

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 544kb
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  • Author :che***
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Introduction - If you have any usage issues, please Google them yourself
synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted
Packet file list
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data_transfer
.............\00001.bmp
.............\00002.bmp
.............\SSDT
.............\....\src
.............\....\...\SSDT.vhd
.............\....\...\SSDT_TB.vhd
.............\....\ssdt.cr.mti
.............\....\ssdt.mpf
.............\....\SSDT_TBZ.vhd
.............\....\transcript
.............\....\vsim.wlf
.............\....\wave.do
.............\....\wave_final_no_zero
.............\....\wave_nozero
.............\....\wave_zero
.............\....\work
.............\....\....\ssdt
.............\....\....\....\rtl.asm
.............\....\....\....\rtl.dat
.............\....\....\....\_primary.dat
.............\....\....\ssdt_tb
.............\....\....\.......\behavior.asm
.............\....\....\.......\behavior.dat
.............\....\....\.......\_primary.dat
.............\....\....\_info
.............\....\复件 SSDT_TB.vhd
.............\SSDT电路的RTL结构图.vsd
.............\两字节插零9FBDH.bmp
.............\两次FS之间的转换.bmp
.............\传送最后插零5FH.bmp
.............\传送最后无零5EH.bmp
.............\同步串行数据发送电路报告.doc
.............\字节中间插零3EH.bmp
.............\字节末尾插零DFH.bmp
.............\综合时序报告.bmp
.............\综合门级报告.bmp
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