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TOKEN_vrilog

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 355kb
  • Downloaded :0次
  • Author :che***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted
Packet file list
(Preview for download)
TOKEN
.....\01读入R1和R2.bmp
.....\02发送R2.BMP
.....\03发送R1.BMP
.....\04发送DATA.bmp
.....\05发送校验位.bmp
.....\06再次读入R1和R2.bmp
.....\07综合结果面积.bmp
.....\08综合结果时序.bmp
.....\RTL结构图.vsd
.....\Token
.....\.....\src
.....\.....\...\TOKEN.vhd
.....\.....\...\TOKEN_TB.vhd
.....\.....\...\transcript
.....\.....\TOKEN.cr.mti
.....\.....\TOKEN.mpf
.....\.....\vsim.wlf
.....\.....\wave.wlf
.....\.....\work
.....\.....\....\token
.....\.....\....\.....\rtl.asm
.....\.....\....\.....\rtl.dat
.....\.....\....\.....\_primary.dat
.....\.....\....\token_tb
.....\.....\....\........\behavior.asm
.....\.....\....\........\behavior.dat
.....\.....\....\........\_primary.dat
.....\.....\....\_info
.....\TOKEN.vhd
.....\TOKEN_TB.vhd
.....\TOKEN发送电路报告.doc
.....\状态图.vsd
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