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TLC5510APhase

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 908kb
  • Downloaded :0次
  • Author :张*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
TLC5510A use of high-speed (20M), scanning waveform, phase difference measurement, Measuring 2 2 TLC5510A waveform.
Packet file list
(Preview for download)
backup
......\cexiang1
......\........\add18.bsf
......\........\add18.v
......\........\Adr4_16.bsf
......\........\Adr4_16.v
......\........\ASIC74573.bsf
......\........\asic74573.v
......\........\BUS_Connect.bsf
......\........\bus_connect.v
......\........\ce_gao.bsf
......\........\ce_gao.v

......\........\cf_waveforms.html
......\........\chufa.bsf
......\........\chufa.v
......\........\cmp_state.ini
......\........\CONTER8.bsf
......\........\CONTER8.v
......\........\core_1c6.asm.rpt
......\........\core_1c6.bdf
......\........\core_1c6.bsf
......\........\core_1c6.cdf
......\........\core_1c6.done
......\........\core_1c6.fit.eqn
......\........\core_1c6.fit.rpt
......\........\core_1c6.fit.summary
......\........\core_1c6.fld
......\........\core_1c6.flow.rpt
......\........\core_1c6.map.eqn
......\........\core_1c6.map.rpt
......\........\core_1c6.map.summary
......\........\core_1c6.pin
......\........\core_1c6.pof
......\........\core_1c6.qpf
......\........\core_1c6.qsf
......\........\core_1c6.qws
......\........\core_1c6.sof
......\........\core_1c6.tan.rpt
......\........\core_1c6.tan.summary
......\........\core_1c6_assignment_defaults.qdf
......\........\data_ctl.bsf
......\........\data_ctl.v
......\........\db
......\........\..\altsyncram_5ur.tdf
......\........\..\altsyncram_aqb1.tdf
......\........\..\altsyncram_r9l.tdf
......\........\..\cntr_419.tdf
......\........\..\cntr_cn8.tdf
......\........\..\core_1c6.asm.qmsg
......\........\..\core_1c6.cbx.xml
......\........\..\core_1c6.cmp.cdb
......\........\..\core_1c6.cmp.hdb
......\........\..\core_1c6.cmp.qrpt
......\........\..\core_1c6.cmp.rdb
......\........\..\core_1c6.cmp.tdb
......\........\..\core_1c6.cmp0.ddb
......\........\..\core_1c6.dbp
......\........\..\core_1c6.db_info
......\........\..\core_1c6.eco.cdb
......\........\..\core_1c6.fit.qmsg
......\........\..\core_1c6.hier_info
......\........\..\core_1c6.hif
......\........\..\core_1c6.map.cdb
......\........\..\core_1c6.map.hdb
......\........\..\core_1c6.map.qmsg
......\........\..\core_1c6.pre_map.cdb
......\........\..\core_1c6.pre_map.hdb
......\........\..\core_1c6.psp
......\........\..\core_1c6.rtlv.hdb
......\........\..\core_1c6.rtlv_sg.cdb
......\........\..\core_1c6.rtlv_sg_swap.cdb
......\........\..\core_1c6.sgdiff.cdb
......\........\..\core_1c6.sgdiff.hdb
......\........\..\core_1c6.signalprobe.cdb
......\........\..\core_1c6.sld_design_entry_dsc.sci
......\........\..\core_1c6.syn_hier_info
......\........\..\core_1c6.tan.qmsg
......\........\..\core_1c60.rtl.mif
......\........\..\core_1c6_cmp.qrpt
......\........\div_10.bsf
......\........\div_10.v
......\........\div_100.bsf
......\........\div_100.v
......\........\div_1000.bsf
......\........\div_1000.v
......\........\fp2.bsf
......\........\fp2.v
......\........\fp_2.bsf
......\........\fp_2.v
......\........\interrupt.v
......\........\pipeline_add_64.bsf
......\........\pipeline_add_64.v
......\........\RAM_1K.bsf
......\........\RAM_1K.v
......\........\RAM_1K_bb.v
......\........\RAM_ADDR.bsf
......\........\RAM_ADDR.v
......\........\ROM_1K.bsf
......\........\ROM_1K.v
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