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  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 336kb
  • Downloaded :0次
  • Author :李***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
spi bus vhdl code Shileshi can use. The hope is to help developers.
Packet file list
(Preview for download)
IP_SPI
......\func_sim.do
......\post_sim.do
......\readme.doc
......\readme.txt
......\sck_logic.vhd
......\spi_control_sm.vhd
......\spi_interface.vhd
......\spi_master.bld
......\spi_master.blx
......\spi_master.chk
......\spi_master.cmd_log
......\spi_master.cxt
......\spi_master.ise
......\spi_master.ise_ISE_Backup
......\spi_master.jed
......\spi_master.log
......\spi_master.lso
......\spi_master.ngc
......\spi_master.ngd
......\spi_master.ngr
......\spi_master.npl
......\spi_master.npl_ISE_Backup
......\spi_master.pad
......\spi_master.prj
......\spi_master.rpt
......\spi_master.stx
......\spi_master.syr
......\spi_master.vhd
......\spi_master.xml
......\spi_master.xst
......\spi_master_build.xml
......\spi_master_pad.csv
......\spi_master_tb.vhd
......\spi_master_timesim.vhd
......\spi_rcv_shift_reg.vhd
......\spi_xmit_shift_reg.vhd
......\tmperr.err
......\uc_interface.vhd
......\upcnt4.vhd
......\upcnt5.vhd
......\wave_color.do
......\wave_post_color.do
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