This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function.

test
....\change.acf
....\change.hif
....\clock.acf
....\clock.fit
....\clock.gdf
....\clock.hex
....\clock.hif
....\clock.mmf
....\clock.ndb
....\clock.pin
....\clock.pof
....\clock.rpt
....\clock.scf
....\clock.snf
....\clock.sof
....\clock.ttf
....\clock1.pin
....\clock1.pof
....\count24.acf
....\count24.fit
....\count24.hif
....\count24.mmf
....\count24.ndb
....\count24.pin
....\count24.pof
....\count24.rpt
....\count24.scf
....\count24.snf
....\COUNT24.sym
....\Count24.vhd
....\count60.acf
....\count60.fit
....\count60.hif
....\count60.mmf
....\count60.ndb
....\count60.pin
....\count60.pof
....\count60.rpt
....\count60.scf
....\count60.snf
....\COUNT60.sym
....\count60.vhd
....\display.acf
....\display.fit
....\display.hif
....\display.mmf
....\display.ndb
....\display.pin
....\display.pof
....\display.rpt
....\display.scf
....\display.snf
....\DISPLAY.sym
....\display.vhd
....\display2.acf
....\display2.fit
....\display2.hif
....\display2.mmf
....\display2.ndb
....\display2.pin
....\display2.pof
....\display2.rpt
....\display2.scf
....\display2.snf
....\DISPLAY2.sym
....\display2.vhd
....\feiwei.acf
....\feiwei.hif
....\feiwei.mmf
....\FeiWei.vhd
....\fenwei.acf
....\fenwei.fit
....\fenwei.hif
....\fenwei.mmf
....\fenwei.ndb
....\fenwei.pin
....\fenwei.pof
....\fenwei.rpt
....\fenwei.scf
....\fenwei.snf
....\FENWEI.sym
....\fenwei.vhd
....\LIB.DLS
....\real24.acf
....\real24.fit
....\real24.gdf
....\real24.hif
....\real24.mmf
....\real24.ndb
....\real24.pin
....\real24.pof
....\real24.rpt
....\real24.scf
....\real24.snf
....\real24.sym
....\real60.acf
....\real60.fit
....\real60.gdf
....\real60.hif

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