based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation

09-03_fangzhen
..............\CNT_N.v
..............\CNT_N_1_TEST.v
..............\CNT_N_2_TEST.v
..............\GEN_CLK_1.v
..............\GEN_CLK_1_TEST.v
..............\GEN_CLK_2.v
..............\GEN_CLK_2_TEST.v
..............\PULSE_NUM_S.v
..............\PULSE_NUM_S_TEST.v

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