Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

edaTimer

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 40kb
  • Downloaded :0次
  • Author :wang****
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
digital clock is the main function Minutes date when the output function and the date and time set for the function , they can point the entire timekeeping functions. Digital Clock Design is the core issue date of the clock automatic conversion function. Automatic identification is the number of days in the control. One can design a structure as shown in the digital clock, the digital clock module, including schools, the number of days in processing module, Minutes module at the time, date and output modules to choose modules. In this study, only a simple figures accurate design, the other part of the next step yet to be improved.
Packet file list
(Preview for download)
刘宇 eda实验报告.doc
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.