16-ahead adder, Verilog HDL

LAC_adder16
...........\cmp_state.ini
...........\db
...........\..\LAC_adder16.asm.qmsg
...........\..\LAC_adder16.cbx.xml
...........\..\LAC_adder16.cmp.cdb
...........\..\LAC_adder16.cmp.hdb
...........\..\LAC_adder16.cmp.qrpt
...........\..\LAC_adder16.cmp.rdb
...........\..\LAC_adder16.cmp.tdb
...........\..\LAC_adder16.cmp0.ddb
...........\..\LAC_adder16.dbp
...........\..\LAC_adder16.db_info
...........\..\LAC_adder16.eco.cdb
...........\..\LAC_adder16.fit.qmsg
...........\..\LAC_adder16.fnsim.hdb
...........\..\LAC_adder16.fnsim.qmsg
...........\..\LAC_adder16.hier_info
...........\..\LAC_adder16.hif
...........\..\LAC_adder16.map.cdb
...........\..\LAC_adder16.map.hdb
...........\..\LAC_adder16.map.qmsg
...........\..\LAC_adder16.pre_map.cdb
...........\..\LAC_adder16.pre_map.hdb
...........\..\LAC_adder16.psp
...........\..\LAC_adder16.rtlv.hdb
...........\..\LAC_adder16.rtlv_sg.cdb
...........\..\LAC_adder16.rtlv_sg_swap.cdb
...........\..\LAC_adder16.sgdiff.cdb
...........\..\LAC_adder16.sgdiff.hdb
...........\..\LAC_adder16.signalprobe.cdb
...........\..\LAC_adder16.sld_design_entry.sci
...........\..\LAC_adder16.sld_design_entry_dsc.sci
...........\..\LAC_adder16.syn_hier_info
...........\..\LAC_adder16.tan.qmsg
...........\..\LAC_adder16_cmp.qrpt
...........\..\LAC_adder16_sim.qrpt
...........\LAC_adder16.asm.rpt
...........\LAC_adder16.done
...........\LAC_adder16.fit.eqn
...........\LAC_adder16.fit.rpt
...........\LAC_adder16.fit.summary
...........\LAC_adder16.flow.rpt
...........\LAC_adder16.map.eqn
...........\LAC_adder16.map.rpt
...........\LAC_adder16.map.summary
...........\LAC_adder16.pin
...........\LAC_adder16.pof
...........\LAC_adder16.qpf
...........\LAC_adder16.qsf
...........\LAC_adder16.qws
...........\LAC_adder16.sim.rpt
...........\LAC_adder16.sof
...........\LAC_adder16.tan.rpt
...........\LAC_adder16.tan.summary
...........\LAC_adder16.v
...........\LAC_adder16.vwf
...........\LAC_adder16_assignment_defaults.qdf
...........\sim.cfg

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