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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 86kb
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  • Author :龙****
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Introduction - If you have any usage issues, please Google them yourself
the realization of the import of a number of routes 16 election a function, the comrades need to be studies, and common progress
Packet file list
(Preview for download)
mux16_1
.......\db
.......\..\mux16_1.cbx.xml
.......\..\mux16_1.cmp.rdb
.......\..\mux16_1.dbp
.......\..\mux16_1.db_info
.......\..\mux16_1.eco.cdb
.......\..\mux16_1.eds_overflow
.......\..\mux16_1.fnsim.cdb
.......\..\mux16_1.fnsim.hdb
.......\..\mux16_1.fnsim.qmsg
.......\..\mux16_1.hier_info
.......\..\mux16_1.hif
.......\..\mux16_1.map.cdb
.......\..\mux16_1.map.hdb
.......\..\mux16_1.map.logdb
.......\..\mux16_1.map.qmsg
.......\..\mux16_1.pre_map.cdb
.......\..\mux16_1.pre_map.hdb
.......\..\mux16_1.psp
.......\..\mux16_1.rtlv.hdb
.......\..\mux16_1.rtlv_sg.cdb
.......\..\mux16_1.rtlv_sg_swap.cdb
.......\..\mux16_1.sgdiff.cdb
.......\..\mux16_1.sgdiff.hdb
.......\..\mux16_1.sim.hdb
.......\..\mux16_1.sim.qmsg
.......\..\mux16_1.sim.rdb
.......\..\mux16_1.sim.vwf
.......\..\mux16_1.sld_design_entry.sci
.......\..\mux16_1.sld_design_entry_dsc.sci
.......\..\mux16_1.syn_hier_info
.......\..\wed.zsf
.......\mux16_1.done
.......\mux16_1.flow.rpt
.......\mux16_1.map.rpt
.......\mux16_1.map.smsg
.......\mux16_1.map.summary
.......\mux16_1.qpf
.......\mux16_1.qsf
.......\mux16_1.qws
.......\mux16_1.sim.rpt
.......\mux16_1.v
.......\mux16_1.vwf
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