Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

simple_clock_VHDL

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 8kb
  • Downloaded :0次
  • Author :
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
(1) with time, minutes and seconds count display, 229 hours for 24, 50 minutes and 60 seconds for the 229. (2) can be reset according to the need, resetting, home spaces, and other functions.
Packet file list
(Preview for download)
简单电子钟VHDL设计.doc
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.