FPGA-CPLD_DesignTool (example7) a friend in need can be downloaded

Example-7-1
...........\Xpower_Demo
...........\...........\prescale_counter
...........\...........\................\.untf
...........\...........\................\automake.log
...........\...........\................\bitgen.ut
...........\...........\................\invchn26.vcd
...........\...........\................\prescale_counter.alf
...........\...........\................\prescale_counter.ana
...........\...........\................\prescale_counter.bgn
...........\...........\................\prescale_counter.bit
...........\...........\................\prescale_counter.bld
...........\...........\................\prescale_counter.cmd_log
...........\...........\................\prescale_counter.dly
...........\...........\................\prescale_counter.drc
...........\...........\................\prescale_counter.jhd
...........\...........\................\prescale_counter.mrp
...........\...........\................\prescale_counter.nc1
...........\...........\................\prescale_counter.ncd
...........\...........\................\prescale_counter.nga
...........\...........\................\prescale_counter.nga_par
...........\...........\................\prescale_counter.ngc
...........\...........\................\prescale_counter.ngd
...........\...........\................\prescale_counter.ngm
...........\...........\................\prescale_counter.ngr
...........\...........\................\prescale_counter.npl
...........\...........\................\prescale_counter.pad
...........\...........\................\prescale_counter.par
...........\...........\................\prescale_counter.pcf
...........\...........\................\prescale_counter.prj
...........\...........\................\prescale_counter.sprj
...........\...........\................\prescale_counter.stx
...........\...........\................\prescale_counter.syr
...........\...........\................\prescale_counter.twr
...........\...........\................\prescale_counter.twx
...........\...........\................\prescale_counter.ut
...........\...........\................\prescale_counter.v
...........\...........\................\prescale_counter.versim_par
...........\...........\................\prescale_counter.xpi
...........\...........\................\prescale_counter_map.ncd
...........\...........\................\prescale_counter_map.ngm
...........\...........\................\prescale_counter_ngdbuild.nav
...........\...........\................\prescale_counter_timesim.sdf
...........\...........\................\prescale_counter_timesim.v
...........\...........\................\prescale_counter_xpwr.xml
...........\...........\................\testbench.jhd
...........\...........\................\testbench.tdo
...........\...........\................\testbench.tf
...........\...........\................\testbench.udo
...........\...........\................\transcript
...........\...........\................\work
...........\...........\................\....\glbl
...........\...........\................\....\....\verilog.asm
...........\...........\................\....\....\_primary.dat
...........\...........\................\....\....\_primary.vhd
...........\...........\................\....\prescale_counter
...........\...........\................\....\................\verilog.asm
...........\...........\................\....\................\_primary.dat
...........\...........\................\....\................\_primary.vhd
...........\...........\................\....\testbench
...........\...........\................\....\.........\verilog.asm
...........\...........\................\....\.........\_primary.dat
...........\...........\................\....\.........\_primary.vhd
...........\...........\................\....\_info
...........\...........\................\_ngo
...........\...........\................\....\netlist.lst
...........\...........\................\__projnav
...........\...........\................\.........\bitgen.rsp
...........\...........\....

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