VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes

数字时钟
........\clock
........\.....\clock.asm.rpt
........\.....\clock.done
........\.....\clock.fit.eqn
........\.....\clock.fit.rpt
........\.....\clock.fit.summary
........\.....\clock.flow.rpt
........\.....\clock.map.eqn
........\.....\clock.map.rpt
........\.....\clock.map.summary
........\.....\clock.pin
........\.....\clock.pof
........\.....\clock.qpf
........\.....\clock.qsf
........\.....\clock.qws
........\.....\clock.tan.rpt
........\.....\clock.tan.summary
........\.....\clock.vhd
........\.....\cmp_state.ini
........\.....\db
........\.....\..\clock.asm.qmsg
........\.....\..\clock.cbx.xml
........\.....\..\clock.cmp.cdb
........\.....\..\clock.cmp.hdb
........\.....\..\clock.cmp.rdb
........\.....\..\clock.cmp.tdb
........\.....\..\clock.cmp0.ddb
........\.....\..\clock.db_info
........\.....\..\clock.eco.cdb
........\.....\..\clock.fit.qmsg
........\.....\..\clock.hier_info
........\.....\..\clock.hif
........\.....\..\clock.map.cdb
........\.....\..\clock.map.hdb
........\.....\..\clock.map.qmsg
........\.....\..\clock.pre_map.cdb
........\.....\..\clock.pre_map.hdb
........\.....\..\clock.psp
........\.....\..\clock.rtlv.hdb
........\.....\..\clock.rtlv_sg.cdb
........\.....\..\clock.rtlv_sg_swap.cdb
........\.....\..\clock.sgdiff.cdb
........\.....\..\clock.sgdiff.hdb
........\.....\..\clock.sld_design_entry.sci
........\.....\..\clock.sld_design_entry_dsc.sci
........\.....\..\clock.syn_hier_info
........\.....\..\clock.tan.qmsg
........\clock.asm.rpt
........\clock.bdf
........\clock.cdf
........\clock.done
........\clock.fit.eqn
........\clock.fit.rpt
........\clock.fit.summary
........\clock.flow.rpt
........\clock.map.eqn
........\clock.map.rpt
........\clock.map.summary
........\clock.pin
........\clock.pof
........\clock.qpf
........\clock.qsf
........\clock.qws
........\clock.sof
........\clock.tan.rpt
........\clock.tan.summary
........\clock_assignment_defaults.qdf
........\cmp_state.ini
........\db
........\..\add_sub_0eh.tdf
........\..\add_sub_9ph.tdf
........\..\add_sub_aph.tdf
........\..\add_sub_bph.tdf
........\..\add_sub_vdh.tdf
........\..\clock.cbx.xml
........\..\clock.cmp.rdb
........\..\clock.db_info
........\..\clock.eco.cdb
........\..\clock.hif
........\..\clock.map.hdb
........\..\clock.map.qmsg
........\..\clock.sld_design_entry.sci
........\..\clock.sld_design_entry_dsc.sci
........\..\clock_cmp.qrpt
........\..\clock_hier_info
........\..\clock_syn_hier_info
........\decode47.bsf
........\decode47.vhd
........\fen1.bsf
........\fen1.vhd
........\fen100.bsf
........\fen100.vhd
........\fen24.bsf
........\fen24.vhd
........\fen60.bsf
........\fen60.vhd
........\sel.bsf
........\sel.vhd

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