FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.

RD1006
......\Document
......\........\rd1006.pdf
......\Source
......\......\i2c.v
......\......\i2c_clk.v
......\......\i2c_rreg.v
......\......\i2c_st.v
......\......\i2c_tbuf.v
......\......\i2c_wreg.v
......\......\transcript
......\TestFixture
......\...........\clk_rst.v
......\...........\i2c_slave.v
......\...........\i2c_tb.v
......\...........\micro.v

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