this device is programmable CPU simulation procedures to share with everyone Rafah

Verilog
.......\verilog
.......\.......\add_one11.v
.......\.......\ALU.v
.......\.......\CU.v
.......\.......\datapath.v
.......\.......\GR6.v
.......\.......\IO.v
.......\.......\mux11x2.v
.......\.......\mux11x3.v
.......\.......\mux3x2.v
.......\.......\mux3x3.v
.......\.......\mux8x3.v
.......\.......\mux8x4.v
.......\.......\opcode.txt
.......\.......\RAM.v
.......\.......\reg3.v
.......\.......\reg8.v
.......\.......\rom.v
.......\.......\SRAM.v
.......\.......\sub_one11.v
.......\.......\TongXin.v
.......\.......\transcript

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