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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.04mb
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  • Author :刘****
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Introduction - If you have any usage issues, please Google them yourself
CCD signal because of its uniqueness, not generally produce a signal source, the procedures used VHDL, ISE as a development platform, have CCD signal simulation of digital signal only after DA conversion can be achieved
Packet file list
(Preview for download)
CCDOUT.bld
CCDOUT.chk
CCDOUT.cmd_log
CCDOUT.cxt
CCDOUT.fdo
CCDOUT.gyd
CCDOUT.ise
CCDOUT.ise_ISE_Backup
CCDOUT.jed
CCDOUT.log
CCDOUT.lso
CCDOUT.mfd
CCDOUT.nga
CCDOUT.ngc
CCDOUT.ngd
CCDOUT.ngr
CCDOUT.ntrc_log
CCDOUT.pad
CCDOUT.pnx
CCDOUT.prj
CCDOUT.rpt
CCDOUT.stx
CCDOUT.syr
CCDOUT.tim
CCDOUT.tspec
CCDOUT.udo
CCDOUT.vhd
CCDOUT.vm6
CCDOUT.xml
CCDOUT.xst
CCDOUT_build.xml
CCDOUT_html
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...........\...\maplogic.js
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