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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 277kb
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  • Author :许****
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Introduction - If you have any usage issues, please Google them yourself
that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
Packet file list
(Preview for download)
pa_ser
......\pa_se.v
......\pa_ser.ise
......\pa_ser.ise_8.1i_backup
......\pa_ser.ise_ISE_Backup
......\pa_se_tst.ant
......\pa_se_tst.fdo
......\pa_se_tst.jhd
......\pa_se_tst.tbw
......\pa_se_tst.tfw
......\pa_se_tst.udo
......\pa_se_tst.xwv
......\pa_se_tst.xwv_bak
......\pa_se_tst_bencher.prj
......\results.txt
......\rev_1
......\.....\Mult_tst.map
......\.....\Mult_tst.tap
......\.....\pa_se.edf
......\.....\pa_se.fse
......\.....\pa_se.htm
......\.....\pa_se.map
......\.....\pa_se.ncf
......\.....\pa_se.sap
......\.....\pa_se.srd
......\.....\pa_se.srm
......\.....\pa_se.srr
......\.....\pa_se.srs
......\.....\pa_se.tap
......\.....\pa_se.tlg
......\.....\rpt_pa_se.areasrr
......\.....\rpt_pa_se_areasrr.htm
......\.....\rpt_se_pa.areasrr
......\.....\rpt_se_pa_areasrr.htm
......\.....\se_pa.edf
......\.....\se_pa.fse
......\.....\se_pa.htm
......\.....\se_pa.map
......\.....\se_pa.ncf
......\.....\se_pa.sap
......\.....\se_pa.srd
......\.....\se_pa.srm
......\.....\se_pa.srr
......\.....\se_pa.srs
......\.....\se_pa.tap
......\.....\se_pa.tlg
......\.....\syntmp
......\.....\......\Mult_tst.plg
......\.....\......\Mult_tst_flink.htm
......\.....\......\Mult_tst_srr.htm
......\.....\......\Mult_tst_toc.htm
......\.....\......\pa_se.msg
......\.....\......\pa_se.plg
......\.....\......\pa_se_flink.htm
......\.....\......\pa_se_srr.htm
......\.....\......\pa_se_toc.htm
......\.....\......\sap.log
......\.....\......\se_pa.msg
......\.....\......\se_pa.plg
......\.....\......\se_pa_flink.htm
......\.....\......\se_pa_srr.htm
......\.....\......\se_pa_toc.htm
......\.....\verif
......\.....\.....\Mult_tst.vif
......\.....\.....\pa_se.vif
......\.....\.....\se_pa.vif
......\se_pa.cmd_log
......\se_pa.lso
......\se_pa.ngc
......\se_pa.ngr
......\se_pa.prj
......\se_pa.stx
......\se_pa.syr
......\se_pa.v
......\se_pa.xst
......\se_pa_sy.prd
......\se_pa_sy.prj
......\se_pa_tst.ant
......\se_pa_tst.jhd
......\se_pa_tst.tbw
......\se_pa_tst.tfw
......\se_pa_tst.xwv
......\se_pa_tst.xwv_bak
......\se_pa_tst_bencher.prj
......\se_pa_vhdl.prj
......\transcript
......\vsim.wlf
......\work
......\....\pa_se
......\....\.....\verilog.asm
......\....\.....\_primary.dat
......\....\.....\_primary.vhd
......\....\pa_se_tst
......\....\.........\verilog.asm
......\....\.........\_primary.dat
......\....\.........\_primary.vhd
......\....\se_pa
......\....\.....\verilog.asm
......\....\.....\_primary.dat
......\....\.....\_primary.vhd
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