using VHDL description line 8 3 degrees decoder lines, the development is in FPGA

74LS138
.......\db
.......\..\LS.asm.qmsg
.......\..\LS.cbx.xml
.......\..\LS.cmp.cdb
.......\..\LS.cmp.hdb
.......\..\LS.cmp.qrpt
.......\..\LS.cmp.rdb
.......\..\LS.cmp.tdb
.......\..\LS.cmp0.ddb
.......\..\LS.dbp
.......\..\LS.db_info
.......\..\LS.eco.cdb
.......\..\LS.eds_overflow
.......\..\LS.fit.qmsg
.......\..\LS.hier_info
.......\..\LS.hif
.......\..\LS.map.cdb
.......\..\LS.map.hdb
.......\..\LS.map.qmsg
.......\..\LS.pre_map.cdb
.......\..\LS.pre_map.hdb
.......\..\LS.psp
.......\..\LS.rpp.qmsg
.......\..\LS.rtlv.hdb
.......\..\LS.rtlv_sg.cdb
.......\..\LS.rtlv_sg_swap.cdb
.......\..\LS.sgate.rvd
.......\..\LS.sgate_sm.rvd
.......\..\LS.sgdiff.cdb
.......\..\LS.sgdiff.hdb
.......\..\LS.signalprobe.cdb
.......\..\LS.sim.hdb
.......\..\LS.sim.qmsg
.......\..\LS.sim.qrpt
.......\..\LS.sim.rdb
.......\..\LS.sim.vwf
.......\..\LS.sld_design_entry.sci
.......\..\LS.sld_design_entry_dsc.sci
.......\..\LS.syn_hier_info
.......\..\LS.tan.qmsg
.......\LS.asm.rpt
.......\LS.done
.......\LS.fit.eqn
.......\LS.fit.rpt
.......\LS.fit.summary
.......\LS.flow.rpt
.......\LS.map.eqn
.......\LS.map.rpt
.......\LS.map.summary
.......\LS.pin
.......\LS.pof
.......\LS.qpf
.......\LS.qsf
.......\LS.qws
.......\LS.sim.rpt
.......\LS.sof
.......\LS.tan.rpt
.......\LS.tan.summary
.......\LS.vhd
.......\LS.vwf

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