verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA/CPLD beginners

数字时钟
........\clock.asm.rpt
........\clock.cdf
........\clock.done
........\clock.fit.eqn
........\clock.fit.rpt
........\clock.fit.summary
........\clock.flow.rpt
........\clock.map.eqn
........\clock.map.rpt
........\clock.map.summary
........\clock.pin
........\clock.pof
........\clock.qpf
........\clock.qsf
........\clock.qws
........\clock.tan.rpt
........\clock.tan.summary
........\clock.v
........\clock.v.bak
........\cmp_state.ini
........\db
........\..\add_sub_bph.tdf
........\..\add_sub_onh.tdf
........\..\clock.asm.qmsg
........\..\clock.cbx.xml
........\..\clock.cmp.cdb
........\..\clock.cmp.hdb
........\..\clock.cmp.rdb
........\..\clock.cmp.tdb
........\..\clock.cmp0.ddb
........\..\clock.db_info
........\..\clock.eco.cdb
........\..\clock.fit.qmsg
........\..\clock.hier_info
........\..\clock.hif
........\..\clock.map.cdb
........\..\clock.map.hdb
........\..\clock.map.qmsg
........\..\clock.pre_map.cdb
........\..\clock.pre_map.hdb
........\..\clock.psp
........\..\clock.rtlv.hdb
........\..\clock.rtlv_sg.cdb
........\..\clock.rtlv_sg_swap.cdb
........\..\clock.sgdiff.cdb
........\..\clock.sgdiff.hdb
........\..\clock.sld_design_entry.sci
........\..\clock.sld_design_entry_dsc.sci
........\..\clock.syn_hier_info
........\..\clock.tan.qmsg
........\..\clock_cmp.qrpt

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