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EP1C3_12_9_DDS

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 41kb
  • Downloaded :0次
  • Author :阳***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
Packet file list
(Preview for download)
EP1C3_12_9_DDS
..............\ADDER10B.VHD
..............\ADDER32B.VHD
..............\cmp_state.ini
..............\DATA
..............\....\LUT10X10.HEX
..............\....\LUT10X10.MIF
..............\dds.asm.rpt
..............\DDS.CDF
..............\dds.done
..............\dds.fit.summary
..............\dds.flow.rpt
..............\dds.map.summary
..............\DDS.PIN
..............\DDS.QPF
..............\DDS.QSF
..............\DDS.QWS
..............\DDS.SOF
..............\dds.tan.summary
..............\DDS.VHD
..............\LUT10X10.HEX
..............\LUT10X10.MIF
..............\README
..............\......\GW48使用readme.txt
..............\REG10B.VHD
..............\REG32B.VHD
..............\SIN_ROM.BSF
..............\SIN_ROM.VHD
..............\STP1.STP
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