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FIFO_Syn

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 25kb
  • Downloaded :0次
  • Author :sheny*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
Packet file list
(Preview for download)
FIFO_Syn
........\FIFO_Buffer.v
........\FIFO_Syn.cr.mti
........\FIFO_Syn.mpf
........\t_FIFO_Buffer.v
........\vsim.wlf
........\work
........\....\@f@i@f@o_@buffer
........\....\................\verilog.asm
........\....\................\_primary.dat
........\....\................\_primary.vhd
........\....\t_@f@i@f@o_@buffer
........\....\..................\verilog.asm
........\....\..................\_primary.dat
........\....\..................\_primary.vhd
........\....\_info
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