This paper presents a root element of the use of 4 Butterfly (m, n)- the counter to reduce the hardware complexity, latency, and power consumption has been involved in the use of conventional adder. And a modified commutator for the FFT algorithm has been described with the use of pipeline transportation for the implementation of continuous input data together with information to reduce memory requirements.

16Point-radix4-FFT
..................\compressor16.v
..................\converter.v
..................\csa.v
..................\fulladder.v
..................\halfadder.v
..................\inv16.v
..................\inverter.v
..................\radixf41.v
..................\stimulus.v
..................\vma.v

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