FPGA to the SRAM write data, VHDL programming

FPGA_write_sram
...............\FPGA
...............\....\automake.log
...............\....\bitgen.ut
...............\....\coregen.log
...............\....\coregen.prj
...............\....\FPGA.dhp
...............\....\FPGA.npl
...............\....\prom.mcs
...............\....\prom.prm
...............\....\prom.sig
...............\....\top.bgn
...............\....\top.bit
...............\....\top.bld
...............\....\top.cmd_log
...............\....\top.drc
...............\....\top.ll
...............\....\top.lso
...............\....\top.mrp
...............\....\top.msd
...............\....\top.msk
...............\....\top.nc1
...............\....\top.ncd
...............\....\top.ngc
...............\....\top.ngd
...............\....\top.ngm
...............\....\top.ngr
...............\....\top.pad
...............\....\top.pad_txt
...............\....\top.par
...............\....\top.pcf
...............\....\top.placed_ncd_tracker
...............\....\top.prj
...............\....\top.rbb
...............\....\top.rbd
...............\....\top.routed_ncd_tracker
...............\....\top.stx
...............\....\top.syr
...............\....\top.twr
...............\....\top.twx
...............\....\top.ut
...............\....\top.vhdl
...............\....\top.xpi
...............\....\top_last_par.ncd
...............\....\top_map.ncd
...............\....\top_map.ngm
...............\....\top_pad.csv
...............\....\top_pad.txt
...............\....\ucf.ucf
...............\....\ucf.ucf.untf
...............\....\xst
...............\....\...\work
...............\....\...\....\hdllib.ref
...............\....\...\....\hdpdeps.ref
...............\....\...\....\sub00
...............\....\...\....\.....\vhpl00.vho
...............\....\...\....\.....\vhpl01.vho
...............\....\_impact.cmd
...............\....\_impact.log
...............\....\_ngo
...............\....\....\netlist.lst
...............\....\__projnav
...............\....\.........\bitgen.rsp
...............\....\.........\coregen.rsp
...............\....\.........\ednTOngd_tcl.rsp
...............\....\.........\FPGA.gfl
...............\....\.........\FPGA_flowplus.gfl
...............\....\.........\map.log
...............\....\.........\nc1TOncd_tcl.rsp
...............\....\.........\par.log
...............\....\.........\parentEditConstraintsTextApp_tcl.rsp
...............\....\.........\posttrc.log
...............\....\.........\runXst_tcl.rsp
...............\....\.........\top.xst
...............\....\.........\top_ncdTOut_tcl.rsp
...............\....\__projnav.log

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