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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 124kb
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  • Author :d***
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Introduction - If you have any usage issues, please Google them yourself
By the VHDL language using the D flip-flop is QUARTUES environment has been tested
Packet file list
(Preview for download)
DFF1
....\db
....\..\dff1.asm.qmsg
....\..\dff1.cbx.xml
....\..\dff1.cmp.bpm
....\..\dff1.cmp.cdb
....\..\dff1.cmp.ecobp
....\..\dff1.cmp.hdb
....\..\dff1.cmp.logdb
....\..\dff1.cmp.rdb
....\..\dff1.cmp.tdb
....\..\dff1.cmp0.ddb
....\..\dff1.cmp_bb.cdb
....\..\dff1.cmp_bb.hdb
....\..\dff1.cmp_bb.logdb
....\..\dff1.cmp_bb.rcf
....\..\dff1.dbp
....\..\dff1.db_info
....\..\dff1.eco.cdb
....\..\dff1.eds_overflow
....\..\dff1.fit.qmsg
....\..\dff1.hier_info
....\..\dff1.hif
....\..\dff1.map.bpm
....\..\dff1.map.cdb
....\..\dff1.map.ecobp
....\..\dff1.map.hdb
....\..\dff1.map.logdb
....\..\dff1.map.qmsg
....\..\dff1.map_bb.cdb
....\..\dff1.map_bb.hdb
....\..\dff1.map_bb.logdb
....\..\dff1.pre_map.cdb
....\..\dff1.pre_map.hdb
....\..\dff1.psp
....\..\dff1.pss
....\..\dff1.rtlv.hdb
....\..\dff1.rtlv_sg.cdb
....\..\dff1.rtlv_sg_swap.cdb
....\..\dff1.sgdiff.cdb
....\..\dff1.sgdiff.hdb
....\..\dff1.signalprobe.cdb
....\..\dff1.sim.cvwf
....\..\dff1.sim.hdb
....\..\dff1.sim.qmsg
....\..\dff1.sim.rdb
....\..\dff1.sld_design_entry.sci
....\..\dff1.sld_design_entry_dsc.sci
....\..\dff1.syn_hier_info
....\..\dff1.tan.qmsg
....\..\prev_cmp_dff1.map.qmsg
....\..\prev_cmp_dff1.sim.qmsg
....\..\wed.wsf
....\dff1.asm.rpt
....\dff1.bsf
....\dff1.done
....\dff1.dpf
....\dff1.fit.rpt
....\dff1.fit.smsg
....\dff1.fit.summary
....\dff1.flow.rpt
....\dff1.map.rpt
....\dff1.map.summary
....\dff1.pin
....\dff1.pof
....\dff1.qpf
....\dff1.qsf
....\dff1.qws
....\dff1.sim.rpt
....\dff1.sof
....\dff1.tan.rpt
....\dff1.tan.summary
....\dff1.vhd
....\dff1.vhd.bak
....\dff1.vwf
....\prev_cmp_dff1.qmsg
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