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vhdl0716

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 8.04mb
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  • Author :杨****
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Introduction - If you have any usage issues, please Google them yourself
ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Packet file list
(Preview for download)
vhdl0716
........\ sin_data_bit.txt
........\0716.dhp
........\0716.ise
........\0716.ise_ISE_Backup
........\accumulator_ctr_dataadjust.vhd
........\adc_control.vhd
........\adc_test.cdc
........\add_accumulator.vhd
........\automake.log
........\baud.vhd
........\bitgen.ut
........\ctr_wide_narrow.ant
........\ctr_wide_narrow.fdo
........\ctr_wide_narrow.jhd
........\ctr_wide_narrow.tbw
........\ctr_wide_narrow.udo
........\ctr_wide_narrow.vhw
........\ctr_wide_narrow.xwv
........\ctr_wide_narrow.xwv_bak
........\ctr_wide_narrow_bencher.prj
........\dataformat_adjust_log.vhd
........\dataformat_adjust_narrowfreq.vhd
........\dataformat_adjust_widefreq.vhd
........\fifo_rs232.edn
........\fifo_rs232.ngo
........\fifo_rs232.sym
........\fifo_rs232.v
........\fifo_rs232.veo
........\fifo_rs232.vhd
........\fifo_rs232.vho
........\fifo_rs232.xco
........\mux_log_wide_narrow.vhd
........\narrow_wide_pulse_generate.cmd_log
........\narrow_wide_pulse_generate.lso
........\narrow_wide_pulse_generate.ngc
........\narrow_wide_pulse_generate.ngr
........\narrow_wide_pulse_generate.prj
........\narrow_wide_pulse_generate.stx
........\narrow_wide_pulse_generate.syr
........\narrow_wide_pulse_generate.vhd
........\narrow_wide_pulse_generate_summary.html
........\pepExtractor.prj
........\readfifo_rs232.vhd
........\reciever.vhd
........\results.txt
........\select_clk.vhd
........\test.ant
........\test.fdo
........\test.jhd
........\test.tbw
........\test.udo
........\test.vhw
........\test.xwv
........\test.xwv_bak
........\test_bencher.prj
........\test_fifo.vhd
........\test_top_wave.vhd
........\test_top_wave_vhd.fdo
........\test_top_wave_vhd.udo
........\top_fmdm_project.bgn
........\top_fmdm_project.bit
........\top_fmdm_project.bld
........\top_fmdm_project.cmd_log
........\top_fmdm_project.drc
........\top_fmdm_project.lso
........\top_fmdm_project.mrp
........\top_fmdm_project.nc1
........\top_fmdm_project.ncd
........\top_fmdm_project.ngc
........\top_fmdm_project.ngd
........\top_fmdm_project.ngm
........\top_fmdm_project.ngr
........\top_fmdm_project.pad
........\top_fmdm_project.pad_txt
........\top_fmdm_project.par
........\top_fmdm_project.pcf
........\top_fmdm_project.placed_ncd_tracker
........\top_fmdm_project.prj
........\top_fmdm_project.routed_ncd_tracker
........\top_fmdm_project.stx
........\top_fmdm_project.syr
........\top_fmdm_project.twr
........\top_fmdm_project.twx
........\top_fmdm_project.ucf
........\top_fmdm_project.ucf.untf
........\top_fmdm_project.ut
........\top_fmdm_project.vhd
........\top_fmdm_project.xpi
........\top_fmdm_project_cs.blc
........\top_fmdm_project_cs.ngc
........\top_fmdm_project_last_par.ncd
........\top_fmdm_project_map.ncd
........\top_fmdm_project_map.ngm
........\top_fmdm_project_pad.csv
........\top_fmdm_project_pad.txt
........\top_fmdm_project_summary.html
........\top_uart.vhd
........\transcript
........\transfer.vhd
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