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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 365kb
  • Downloaded :0次
  • Author :居***
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Introduction - If you have any usage issues, please Google them yourself
Applicable to FPGA-SOPC area to add components, such as COMPNENT
Packet file list
(Preview for download)
ProjNav
.......\automake.log
.......\behavioral_sim.do
.......\glbl.v
.......\KeypadScan.bak
.......\KeypadScan.bld
.......\KeypadScan.cel
.......\KeypadScan.cmd_log
.......\KeypadScan.cxt
.......\KeypadScan.gyd
.......\KeypadScan.lfp
.......\KeypadScan.log
.......\KeypadScan.lso
.......\KeypadScan.mfd
.......\KeypadScan.nga
.......\KeypadScan.ngc
.......\KeypadScan.ngd
.......\KeypadScan.ngr
.......\KeypadScan.par_nlf
.......\KeypadScan.pnx
.......\KeypadScan.prj
.......\KeypadScan.rpt
.......\KeypadScan.stx
.......\KeypadScan.syr
.......\KeypadScan.tspec
.......\KeypadScan.ucf
.......\KeypadScan.ucf.untf
.......\KeypadScan.v
.......\KeypadScan.vcd
.......\KeypadScan.versim_par
.......\KeypadScan.vm6
.......\KeypadScan.xml
.......\KeypadScan._hrpt
.......\KeypadScan_build.xml
.......\KeypadScan_pad.csv
.......\KeypadScan_tb_v_tf.fdo
.......\KeypadScan_tb_v_tf.tdo
.......\KeypadScan_tb_v_tf.udo
.......\KeypadScan_timesim.nlf
.......\KeypadScan_timesim.sdf
.......\KeypadScan_timesim.v
.......\KeypadScan_vhdl.prj
.......\post_fit_sim.do
.......\ProjNav.dhp
.......\ProjNav.npl
.......\t1.dat
.......\t1.phd
.......\t55.dat
.......\t55.phd
.......\t6.dat
.......\t6.phd
.......\tb.asv
.......\tb.bak
.......\tb.v
.......\tmperr.err
.......\transcript
.......\userlang.tpl
.......\vsim.wlf
.......\wave.do
.......\wave_timing.do
.......\work
.......\....\@keypad@scan
.......\....\............\verilog.asm
.......\....\............\_primary.dat
.......\....\............\_primary.vhd
.......\....\@keypad@scan_tb_v_tf
.......\....\....................\verilog.asm
.......\....\....................\_primary.dat
.......\....\....................\_primary.vhd
.......\....\glbl
.......\....\....\verilog.asm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\_info
.......\xst
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\vlg4F
.......\...\....\.....\KeypadScan.bin
.......\_ngo
.......\....\netlist.lst
.......\_pace.ucf
.......\__projnav
.......\.........\KeypadScan.xst
.......\.........\KeypadScan_edfTOngd_tcl.rsp
.......\.........\parentAssignPackagePinsApp_tcl.rsp
.......\.........\parentCreateTimingConstraintsApp_tcl.rsp
.......\.........\parentEditConstraintsTextApp_tcl.rsp
.......\.........\ProjNav.gfl
.......\.........\ProjNav_flowplus.gfl
.......\.........\runXst_tcl.rsp
.......\__projnav.log
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