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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 808kb
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  • Author :liq****
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Introduction - If you have any usage issues, please Google them yourself
FPGA-based platform, to achieve a direct digital frequency synthesis.
Packet file list
(Preview for download)
DDS
...\Adder10B.v
...\Adder32B.v
...\db
...\..\altsyncram_66f2.tdf
...\..\altsyncram_ha91.tdf
...\..\DDS.asm.qmsg
...\..\DDS.asm_labs.ddb
...\..\DDS.cbx.xml
...\..\DDS.cmp.cdb
...\..\DDS.cmp.hdb
...\..\DDS.cmp.kpt
...\..\DDS.cmp.logdb
...\..\DDS.cmp.rdb
...\..\DDS.cmp.tdb
...\..\DDS.cmp0.ddb
...\..\DDS.cmp2.ddb
...\..\DDS.dbp
...\..\DDS.db_info
...\..\DDS.eco.cdb
...\..\DDS.eds_overflow
...\..\DDS.fit.qmsg
...\..\DDS.hier_info
...\..\DDS.hif
...\..\DDS.map.cdb
...\..\DDS.map.hdb
...\..\DDS.map.logdb
...\..\DDS.map.qmsg
...\..\DDS.pre_map.cdb
...\..\DDS.pre_map.hdb
...\..\DDS.psp
...\..\DDS.pss
...\..\DDS.rpp.qmsg
...\..\DDS.rtlv.hdb
...\..\DDS.rtlv_sg.cdb
...\..\DDS.rtlv_sg_swap.cdb
...\..\DDS.sgate.rvd
...\..\DDS.sgate_sm.rvd
...\..\DDS.sgdiff.cdb
...\..\DDS.sgdiff.hdb
...\..\DDS.signalprobe.cdb
...\..\DDS.sim.hdb
...\..\DDS.sim.qmsg
...\..\DDS.sim.rdb
...\..\DDS.sim.vwf
...\..\DDS.sld_design_entry.sci
...\..\DDS.sld_design_entry_dsc.sci
...\..\DDS.syn_hier_info
...\..\DDS.tan.qmsg
...\..\decode_aoi.tdf
...\..\wed.zsf
...\DDS.asm.rpt
...\DDS.cr.mti
...\DDS.done
...\DDS.fit.rpt
...\DDS.fit.smsg
...\DDS.fit.summary
...\DDS.flow.rpt
...\DDS.map.rpt
...\DDS.map.summary
...\DDS.pin
...\DDS.pof
...\DDS.qpf
...\DDS.qsf
...\DDS.qws
...\DDS.sim.rpt
...\DDS.sof
...\DDS.tan.rpt
...\DDS.tan.summary
...\DDS.v
...\DDS.vwf
...\modelsim
...\REG10B.v
...\REG32B.v
...\Sin_rom.mif
...\Sin_rom.v
DDS.v
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