Five POSPHY LEVEL3 Verilog circuit description can be integrated, has been tested.

POS_PHY_RTL
...........\16ch_to_4ch_or_1ch_pl3
...........\......................\link_phy_pl3.v
...........\......................\pmc3386_tx_pl3.v
...........\......................\pmc5382_rx_pl3.v
...........\......................\pmc5382_to_pmc3386_pl3.v
...........\......................\rx_pkt_fifo37x16.v
...........\......................\rx_pkt_fifo_pro.v
...........\......................\rx_pkt_ram1024x2.v
...........\......................\rx_pkt_ram1024x36.v
...........\......................\rx_pkt_ram_pro.v
...........\......................\tx_pkt_fifo37x64.v
...........\link_phy_slave
...........\..............\generic_adjustments.txt
...........\..............\link_phy_pl3.bsf
...........\..............\link_phy_pl3.cmp
...........\..............\link_phy_pl3.html
...........\..............\link_phy_pl3.inc
...........\..............\link_phy_pl3.v
...........\..............\link_phy_pl3.vo
...........\..............\link_phy_pl3_bb.v
...........\..............\link_phy_pl3_inst.v
...........\m_bus
...........\.....\m_bus.v
...........\pl3_fpga_top
...........\............\define.v
...........\............\pl3_fpga_top.v

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