VHDL to achieve 50 duty cycle. And is odd-numbered sub-frequency.

div3
....\cmp_state.ini
....\db
....\..\div3.asm.qmsg
....\..\div3.cbx.xml
....\..\div3.cmp.cdb
....\..\div3.cmp.hdb
....\..\div3.cmp.rdb
....\..\div3.cmp.tdb
....\..\div3.cmp0.ddb
....\..\div3.db_info
....\..\div3.eco.cdb
....\..\div3.eds_overflow
....\..\div3.fit.qmsg
....\..\div3.hier_info
....\..\div3.hif
....\..\div3.map.cdb
....\..\div3.map.hdb
....\..\div3.map.qmsg
....\..\div3.pre_map.cdb
....\..\div3.pre_map.hdb
....\..\div3.psp
....\..\div3.rtlv.hdb
....\..\div3.rtlv_sg.cdb
....\..\div3.rtlv_sg_swap.cdb
....\..\div3.sgdiff.cdb
....\..\div3.sgdiff.hdb
....\..\div3.signalprobe.cdb
....\..\div3.sim.hdb
....\..\div3.sim.qmsg
....\..\div3.sim.rdb
....\..\div3.sim.vwf
....\..\div3.sld_design_entry.sci
....\..\div3.sld_design_entry_dsc.sci
....\..\div3.syn_hier_info
....\..\div3.tan.qmsg
....\..\div3_cmp.qrpt
....\..\div3_sim.qrpt
....\div3.asm.rpt
....\div3.done
....\div3.fit.eqn
....\div3.fit.rpt
....\div3.fit.summary
....\div3.flow.rpt
....\div3.map.eqn
....\div3.map.rpt
....\div3.map.summary
....\div3.pin
....\div3.pof
....\div3.qpf
....\div3.qsf
....\div3.qws
....\div3.sim.rpt
....\div3.sof
....\div3.tan.rpt
....\div3.tan.summary
....\div3.vhd
....\div3.vwf

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