it about using veriolog complement some project,thanks!

verilog_study
.............\1.v
.............\alu(use always).v
.............\BLOCKING.V
.............\compare.v
.............\compare_test.v
.............\compare_test.v.bak
.............\division--.v
.............\division.v
.............\emob_module.v
.............\first.v
.............\FSM.V
.............\function.v
.............\half_clk.v
.............\half_clk_test.v
.............\task.v
.............\test.v
.............\writing.v

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