sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac

db
..\prev_cmp_test.asm.qmsg
..\prev_cmp_test.fit.qmsg
..\prev_cmp_test.map.qmsg
..\prev_cmp_test.sim.qmsg
..\prev_cmp_test.tan.qmsg
..\rom0_generator_sin_2863329b.hdl.mif
..\test.asm.qmsg
..\test.cbx.xml
..\test.cmp.bpm
..\test.cmp.cdb
..\test.cmp.ecobp
..\test.cmp.hdb
..\test.cmp.logdb
..\test.cmp.rdb
..\test.cmp.tdb
..\test.cmp0.ddb
..\test.cmp_bb.cdb
..\test.cmp_bb.hdb
..\test.cmp_bb.logdb
..\test.cmp_bb.rcf
..\test.dbp
..\test.db_info
..\test.eco.cdb
..\test.eds_overflow
..\test.fit.qmsg
..\test.hier_info
..\test.hif
..\test.map.bpm
..\test.map.cdb
..\test.map.ecobp
..\test.map.hdb
..\test.map.logdb
..\test.map.qmsg
..\test.map_bb.cdb
..\test.map_bb.hdb
..\test.map_bb.logdb
..\test.pre_map.cdb
..\test.pre_map.hdb
..\test.psp
..\test.pss
..\test.rpp.qmsg
..\test.rtlv.hdb
..\test.rtlv_sg.cdb
..\test.rtlv_sg_swap.cdb
..\test.sgate.rvd
..\test.sgate_sm.rvd
..\test.sgdiff.cdb
..\test.sgdiff.hdb
..\test.signalprobe.cdb
..\test.sim.cvwf
..\test.sim.hdb
..\test.sim.qmsg
..\test.sim.rdb
..\test.sld_design_entry.sci
..\test.sld_design_entry_dsc.sci
..\test.syn_hier_info
..\test.tan.qmsg
..\wed.wsf
generator.bsf
generator.vhd
generator.vhd.bak
generator_acc6.vhd
generator_acc6.vhd.bak
generator_adder.vhd
generator_adder.vhd.bak
generator_and2.vhd
generator_mux.vhd
generator_reg6.vhd
generator_reg6.vhd.bak
generator_reg8.vhd
generator_sin.vhd
generator_sin.vhd.bak
prev_cmp_test.qmsg
test.asm.rpt
test.bdf
test.done
test.fit.rpt
test.fit.summary
test.flow.rpt
test.map.rpt
test.map.summary
test.pin
test.pof
test.qpf
test.qsf
test.sim.rpt
test.sof
test.tan.rpt
test.tan.summary
test.vwf

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