verilog HDL interface test source code, more practical.

接口实验
........\7段数码管
........\.........\seg71
........\.........\.....\.xhdl3.xref
........\.........\.....\cmp_state.ini
........\.........\.....\db
........\.........\.....\..\seg71.asm.qmsg
........\.........\.....\..\seg71.cbx.xml
........\.........\.....\..\seg71.cmp.cdb
........\.........\.....\..\seg71.cmp.hdb
........\.........\.....\..\seg71.cmp.rdb
........\.........\.....\..\seg71.cmp.tdb
........\.........\.....\..\seg71.cmp0.ddb
........\.........\.....\..\seg71.db_info
........\.........\.....\..\seg71.eco.cdb
........\.........\.....\..\seg71.fit.qmsg
........\.........\.....\..\seg71.hier_info
........\.........\.....\..\seg71.hif
........\.........\.....\..\seg71.map.cdb
........\.........\.....\..\seg71.map.hdb
........\.........\.....\..\seg71.map.qmsg
........\.........\.....\..\seg71.pre_map.cdb
........\.........\.....\..\seg71.pre_map.hdb
........\.........\.....\..\seg71.psp
........\.........\.....\..\seg71.rtlv.hdb
........\.........\.....\..\seg71.rtlv_sg.cdb
........\.........\.....\..\seg71.rtlv_sg_swap.cdb
........\.........\.....\..\seg71.sgdiff.cdb
........\.........\.....\..\seg71.sgdiff.hdb
........\.........\.....\..\seg71.sld_design_entry.sci
........\.........\.....\..\seg71.sld_design_entry_dsc.sci
........\.........\.....\..\seg71.syn_hier_info
........\.........\.....\..\seg71.tan.qmsg
........\.........\.....\..\seg71_cmp.qrpt
........\.........\.....\seg71.asm.rpt
........\.........\.....\seg71.done
........\.........\.....\seg71.fit.eqn
........\.........\.....\seg71.fit.rpt
........\.........\.....\seg71.fit.summary
........\.........\.....\seg71.flow.rpt
........\.........\.....\seg71.map.eqn
........\.........\.....\seg71.map.rpt
........\.........\.....\seg71.map.summary
........\.........\.....\seg71.pin
........\.........\.....\seg71.pof
........\.........\.....\seg71.qpf
........\.........\.....\seg71.qsf
........\.........\.....\seg71.qws
........\.........\.....\seg71.tan.rpt
........\.........\.....\seg71.tan.summary
........\.........\.....\seg71.v
........\.........\.....\seg71.v.bak
........\i2c总线
........\.......\.xhdl3.xref
........\.......\cmp_state.ini
........\.......\db
........\.......\..\add_sub_5ph.tdf
........\.......\..\add_sub_6ph.tdf
........\.......\..\add_sub_dph.tdf
........\.......\..\add_sub_rnh.tdf
........\.......\..\i2c.asm.qmsg
........\.......\..\i2c.cbx.xml
........\.......\..\i2c.cmp.cdb
........\.......\..\i2c.cmp.hdb
........\.......\..\i2c.cmp.rdb
........\.......\..\i2c.cmp.tdb
........\.......\..\i2c.cmp0.ddb
........\.......\..\i2c.db_info
........\.......\..\i2c.eco.cdb
........\.......\..\i2c.fit.qmsg
........\.......\..\i2c.hier_info
........\.......\..\i2c.hif
........\.......\..\i2c.map.cdb
........\.......\..\i2c.map.hdb
........\.......\..\i2c.map.qmsg
........\.......\..\i2c.pre_map.cdb
........\.......\..\i2c.pre_map.hdb
........\.......\..\i2c.psp
........\.......\..\i2c.rtlv.hdb
........\.......\..\i2c.rtlv_sg.cdb
........\.......\..\i2c.rtlv_sg_swap.cdb
........\.......\..\i2c.sgdiff.cdb
........\.......\..\i2c.sgdiff.hdb
........\.......\..\i2c.sld_design_entry.sci
........\.......\..\i2c.sld_design_entry_dsc.sci
........\.......\..\i2c.smp_dump.txt
........\.......\..\i2c.syn_hier_info
........\.......\..\i2c.tan.qmsg
........\.......\..\i2c_cmp.qrpt
........\.......\i2c.asm.rpt
........\.......\i2c.cdf
........\.......\i2c.done
........\.......\i2c.fit.eqn
........\.......\i2c.fit.rpt
........\.......\i2c.fit.summary
........\.......\i2c.fld
........\.......\i2c.flow.rpt
........\.......\i2c.map.eqn
........\.......\i2c.map.rpt
........\.......\i2c.map.summary

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