FPGA ep1c6 of the usb-source experiment, the experimental validation properly used, we can give it a try Oh

TestUSB
.......\cmp_state.ini
.......\db
.......\..\TestUSB.asm.qmsg
.......\..\TestUSB.cmp.cdb
.......\..\TestUSB.cmp.ddb
.......\..\TestUSB.cmp.hdb
.......\..\TestUSB.cmp.rdb
.......\..\TestUSB.cmp.tdb
.......\..\TestUSB.cmp0.ddb
.......\..\TestUSB.db_info
.......\..\TestUSB.eco.cdb
.......\..\TestUSB.fit.qmsg
.......\..\TestUSB.hier_info
.......\..\TestUSB.hif
.......\..\TestUSB.icc
.......\..\TestUSB.map.cdb
.......\..\TestUSB.map.hdb
.......\..\TestUSB.map.qmsg
.......\..\TestUSB.pre_map.cdb
.......\..\TestUSB.pre_map.hdb
.......\..\TestUSB.psp
.......\..\TestUSB.rtlv.hdb
.......\..\TestUSB.rtlv_sg.cdb
.......\..\TestUSB.rtlv_sg_swap.cdb
.......\..\TestUSB.sgdiff.cdb
.......\..\TestUSB.sgdiff.hdb
.......\..\TestUSB.signalprobe.cdb
.......\..\TestUSB.sld_design_entry.sci
.......\..\TestUSB.sld_design_entry_dsc.sci
.......\..\TestUSB.syn_hier_info
.......\..\TestUSB.tan.qmsg
.......\..\TestUSB_cmp.qrpt
.......\Setup.tcl
.......\TestUSB.asm.rpt
.......\TestUSB.done
.......\TestUSB.fit.eqn
.......\TestUSB.fit.rpt
.......\TestUSB.fit.summary
.......\TestUSB.flow.rpt
.......\TestUSB.map.eqn
.......\TestUSB.map.rpt
.......\TestUSB.map.summary
.......\TestUSB.pin
.......\TestUSB.pof
.......\TestUSB.qpf
.......\TestUSB.qsf
.......\TestUSB.qws
.......\TestUSB.sof
.......\TestUSB.tan.rpt
.......\TestUSB.tan.summary
.......\TestUSB.v
.......\usb_loop.v

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