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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
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Introduction - If you have any usage issues, please Google them yourself
PS/2 communication protocol is a bi-directional synchronous serial communication protocol. Communication at both ends through the Clock (the clock pin) synchronization, and Data (data pin) to exchange data. If you want to inhibit any of the parties the other party of communication, just to Clock (Clock feet) down low. The general transmission of data between two devices of the maximum clock frequency is 33kHz, the majority of PS/2 devices work in the 10 ~ 20kHz. Recommended value of around 15kHz, which means, Clock (Clock feet) high, low for the duration of 40μs. Each data frame contains 11 ~ 12-bit.
Packet file list
(Preview for download)
ps2.txt
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