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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 80kb
  • Downloaded :0次
  • Author :谢****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
jk flip-flop, try to edit their own, using state machine to achieve, you can
Packet file list
(Preview for download)
jkchu
.....\db
.....\..\jkchu.asm.qmsg
.....\..\jkchu.cbx.xml
.....\..\jkchu.cmp.cdb
.....\..\jkchu.cmp.hdb
.....\..\jkchu.cmp.logdb
.....\..\jkchu.cmp.rdb
.....\..\jkchu.cmp.tdb
.....\..\jkchu.cmp0.ddb
.....\..\jkchu.dbp
.....\..\jkchu.db_info
.....\..\jkchu.eco.cdb
.....\..\jkchu.eds_overflow
.....\..\jkchu.fit.qmsg
.....\..\jkchu.hier_info
.....\..\jkchu.hif
.....\..\jkchu.map.cdb
.....\..\jkchu.map.hdb
.....\..\jkchu.map.logdb
.....\..\jkchu.map.qmsg
.....\..\jkchu.pre_map.cdb
.....\..\jkchu.pre_map.hdb
.....\..\jkchu.psp
.....\..\jkchu.pss
.....\..\jkchu.rtlv.hdb
.....\..\jkchu.rtlv_sg.cdb
.....\..\jkchu.rtlv_sg_swap.cdb
.....\..\jkchu.sgdiff.cdb
.....\..\jkchu.sgdiff.hdb
.....\..\jkchu.sim.cvwf
.....\..\jkchu.sim.hdb
.....\..\jkchu.sim.qmsg
.....\..\jkchu.sim.rdb
.....\..\jkchu.sld_design_entry.sci
.....\..\jkchu.sld_design_entry_dsc.sci
.....\..\jkchu.syn_hier_info
.....\..\jkchu.tan.qmsg
.....\..\wed.wsf
.....\jkchu.asm.rpt
.....\jkchu.done
.....\jkchu.fit.rpt
.....\jkchu.fit.summary
.....\jkchu.flow.rpt
.....\jkchu.map.rpt
.....\jkchu.map.summary
.....\jkchu.pin
.....\jkchu.pof
.....\jkchu.qpf
.....\jkchu.qsf
.....\jkchu.qws
.....\jkchu.sim.rpt
.....\jkchu.tan.rpt
.....\jkchu.tan.summary
.....\jkchu.vhd
.....\jkchu.vwf
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