Advanced Digital Design Verilog HDL source _chapter5

VerilogHDL_advanced_digital_design_code_Ch5
...........................................\adder_task.v
...........................................\ADDVB_Models_5.doc
...........................................\add_4cycle.v
...........................................\AOI_5_CA0.v
...........................................\AOI_5_CA1.v
...........................................\AOI_5_CA2.v
...........................................\AOI_5_CA3.v
...........................................\arithmetic_unit.v
...........................................\asynch_df_behav.v
...........................................\Auto_LFSR_ALGO.v
...........................................\Auto_LFSR_Param.v
...........................................\Auto_LFSR_RTL.v
...........................................\barrel_shifter.v
...........................................\comparator.v
...........................................\compare_2_algo.v
...........................................\compare_2_CA0.v
...........................................\compare_2_CA1.txt
...........................................\compare_2_CA1.v
...........................................\compare_2_ROM.v
...........................................\compare_2_RTL.v
...........................................\compare_32_CA.v
...........................................\decoder.v
...........................................\df_behav.v
...........................................\encoder.v
...........................................\find_first_one.v
...........................................\Hex_Keypad_Grayhill_072.v
...........................................\Latch_CA.v
...........................................\Latch_Rbar_CA.v
...........................................\Majority.v
...........................................\Majority_4b.v
...........................................\Mux_4_32_CA.v
...........................................\Mux_4_32_case.v
...........................................\Mux_4_32_if.v
...........................................\Par_load_reg4.v
...........................................\pipe_2stage.v
...........................................\priority.v
...........................................\Register_File.v
...........................................\ring_counter.v
...........................................\Row_Signal.v
...........................................\Seven_Seg_Display.v
...........................................\shiftreg_nb.v
...........................................\shiftreg_PA.v
...........................................\shiftreg_PA_rev.v
...........................................\Shift_reg4.v
...........................................\shift_reg_PA.v
...........................................\Synchronizer.v
...........................................\synchro_2.v
...........................................\tr_latch.v
...........................................\t_AOI_5_CA1.v
...........................................\t_AOI_5_CA2.v
...........................................\t_Bin_Cnt_Part_RTL.v
...........................................\t_Hex_Keypad_Grayhill_072.v
...........................................\t_Latch_CA.v
...........................................\t_Latch_Rbar_CA.v
...........................................\Universal_Shift_Reg.v
...........................................\Universal_Shift_Register.v
...........................................\up_down_counter.v
...........................................\Up_Down_Implicit1.v
...........................................\word_aligner.v
...........................................\_vti_cnf
...........................................\........\adder_task.v
...........................................\........\ADDVB_Models_5.doc
...........................................\........\add_4cycle.v
...........................................\........\AOI_5_CA0.v
...........................................\........\AOI_5_CA1.v
...........................................\........\AOI_5_CA2.v
...........................................\........\AOI_5_CA3.v
.................

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